1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and in particular, to an input circuit for a semiconductor memory apparatus and a control method thereof.
2. Related Art
A conventional input circuit for a semiconductor memory apparatus is illustrated in the block diagram of FIG. 1. Referring to FIG. 1, an input circuit for a conventional semiconductor memory apparatus includes a chip-selection-signal latch circuit 1, a first command/address latch circuit 2, a second command/address latch circuit 3, and a third command/address latch circuit 4.
The chip-selection-signal latch circuit 1 is configured to latch a chip selection signal “/CS” according to a clock signal “CLK”. The chip-selection-signal latch circuit 1 includes a CARR latch. The CARR latch is configured to latch an input signal at a rising edge of the clock signal “CLK”.
The first command/address latch circuit 2 is configured to latch command/address signals “CA<0:#>” according to the clock signal “CLK”. The first command/address latch circuit 2 includes a plurality of CARR latches. A command and address may be input through separate pins or a common pin according to the kind of semiconductor memory apparatus. The circuit shown in FIG. 1 is an example in which a command and address are input through a common pin.
The second command/address latch circuit 3 is configured to latch output signals “ICARR<0:#>” of the first command/address latch circuit 2 according to the clock signal “CLK”. The second command/address latch circuit 3 includes a plurality of CARF latches. Each of the CARF latches is configured to latch an input signal at a falling edge of the clock signal “CLK”.
The third command/address latch circuit 4 is configured to latch the command/address signals “CA<0:#>” according to the clock signal “CLK”. The third command/address latch circuit 4 includes a plurality of CAFF latches. Each of the CAFF latches is configured to latch an input signal at a falling edge of the clock signal “CLK”.
FIG. 2 is a timing chart illustrating the operation of the input circuit of FIG. 1.
Referring to a signal “ICSBRR”, it can be seen that the chip-selection-signal latch circuit 1 latches the chip selection signal “/CS” at a rising edge of the clock signal “CLK”. Referring to a signal “ICARR<0>”, it can be seen that the first command/address latch circuit 2 latches the command/address signal “CA<0>” at a rising edge of the clock signal “CLK”. Referring to a signal “ICARF<0>”, it can be seen that the second command/address latch circuit 3 latches the output signal “ICARR<0>” of the first command/address latch circuit 2 at a falling edge of the clock signal “CLK”. Referring to a signal “ICAFF<0>”, it can be seen that the third command/address latch circuit 4 latches the command/address signal “CA<0>” at a falling edge of the clock signal “CLK”.
Thus, even in a non-operation (NOP) mode in which the semiconductor memory apparatus does not perform an active operation, such as a read or write operation, all latched signals are toggled.
FIG. 2 shows only certain of three latched signals, i.e., “ICSBRR”, “ICARR<0>”, “ICARF<0>”, and “ICAFF<0>”, however, all the latched signals “ICSBRR”, “ICARR<0:#>”, “ICARF<0:#>”, and “ICAFF<0:#>” are toggled in the same manner. Toggling of the latched signals result from the operations of all the latch circuits 1 to 4, which may cause unnecessary power consumption in the NOP mode.
Accordingly, excessive power consumption can occur in a conventional input circuit due to the unnecessary toggling of various signals even in the NOP mode. It will be understood that power consumption is a major concern for semiconductor memory apparatus and the devices they go into. Therefore, it is often essential to minimize the amount of power consumption.